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Reliability aspects of chip to chip interconnections 3D interconnection technologies significantly improve the versatility of integrated circuits since different functions can fit in smaller space by chip stacking. This allows further implementation of integrated chips in daily objects. Key end user applications are Internet of Things, automotive, mobile internet and wearable device. The automotive segment demands 3D interconnection technologies to endure harsh environments such as temperatures up to 200 °C and currents in the magnitude of 1 A. The performance of µ-bumps stacked on copper pillars, which enable the electrical connection between two chips, was tested in such environments. The interconnection itself consists of different metal layers. The biggest reliability concern is the solder layer because after processing voids may form inside this layer. Moreover, intermetallic compounds with copper and nickel at the interface regions may build up as well. This investigation aims at the understanding of the evolution of the voids and intermetallic compounds during high temperature storage and electromigration stress testing. Cross sections and energy dispersive X-ray spectroscopy analysis are performed before and after the stress tests in order to measure the areas of the voids and intermetallic compound layers. The size measurements are correlated to the monitored resistance changes during the tests allowing the quantification of the kinetics of the two processes. |