Institute of Solid State Physics


SS22WS22SS23WS23SS24WS24      Guidelines for Master Students

Influence of the On-Chip Signal-Metallization Routing Topology on Self-Heating in Integrated Power Technologies
Christian Kovacs
11:15 - 12:15 Wednesday 15 January 2020 PH 01 150

Today’s state-of-the-art integrated bipolar-CMOS-DMOS (BCD) power technologies employ highly optimized DMOS transistors with extremely low area-specific on-resistance. This ensures high current capability at minimum area requirements, however, this comes at the expense of increased thermal impedance leading to increased self-heating of the device. Elevated operating temperatures deteriorate device performance; can lead to decreased lifetime and even catastrophic failure due to thermal runaway. The main factors influencing self-heating during switching events in the millisecond and sub-millisecond regime are the thermal conductivity and thermal capacity of the on-chip metallization.

Previous works investigated the robustness of DMOS transistors with and without a thick power metallization layer, the influence of the number of metal layers between the active area of a DMOS device and the thick power metal layer, as well as via density for vertical heat transport. The aim of my thesis is to investigate the influence and possible benefits of optimized routing topologies of the signal metal layers on the thermal behaviour of large DMOS devices in BCD technologies with the help of thermal FEM simulations.